1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having a signal processor which processes signals read from a recording medium such as a magnetic disk. The signal processor includes a user data processing circuit having an A/D converter and a maximum likelihood decoder, and a servo data processing circuit which has an integrating circuit.
2. Description of the Related Art
There is a demand for a faster reading/writing speed for semiconductor integrated circuit devices, which process a digital signal associated with data read from a magnetic disk. Therefore, it is necessary to improve the operation speeds of a user data processing circuit and a servo data processing circuit which are used in such semiconductor integrated circuit devices.
A system for processing signals from a magnetic disk or other communication system decodes reception signals, using a maximum likelihood decoder, which performs maximum likelihood decoding, as one type of decoding means. In a communication system which transfers information in the form of a finite signal series, there are a plurality of transmission signal series which have probably been transmitted in association with one reception signal series. According to the maximum likelihood decoding, the reception side determines a transmission signal which is considered most appropriate based on some evaluation standards. A reception signal is associated with a transmission signal series in accordance with the decoding rules.
When a transmission signal which is not specified by the decoding rules is sent, a decoding error occurs. Given that Yi represents a reception signal series and X(Yi) represents a corresponding transmission signal series. When a transmission signal series X(Yi) has actually been transmitted and is received as a reception signal series Yi, no decoding error occurs. Given that the probability that such a event occurs is P(X(Yi), Yi), the probability PE that a decoding error occurs is expressed by the following equation:       P    E    =                    ∑        i            ⁢              P        ⁢                  {                                    X              ⁡                              (                Yi                )                                      ,            Yi                    }                      =          1      -                        ∑          i                ⁢                              {                          X              ⁡                              (                Yi                )                                      }                    ⁢          P          ⁢                      {                          Yi              |                              X                ⁡                                  (                  Yi                  )                                                      }                              
Assuming that the probabilities of occurrence of transmission signal series are all the same, P(X(Yi)) becomes constant in any decoding rule. The minimum probability PE is therefore acquired by selecting X(Yi) which maximizes P(YiX(Yi)) with respect to Yi as a transmission signal series. Maximum likelihood decoding is carried out in this manner. A maximum likelihood decoder which executes this maximum likelihood decoding includes a plurality of metric arithmetic operation circuits. Each metric arithmetic operation circuit performs an operation on a transmission signal series X(Yi) and, based on the arithmetic operation result, selects transmission data corresponding to the transmission signal series X(Yi) from expected values of the transmission data written in a pass memory.
FIG. 1 is a block diagram showing a conventional maximum likelihood decoder. The maximum likelihood decoder has first to fourth metric arithmetic operation circuits 1a to 1d each having two inputs to respectively receive two digital signals A1 and A2, B1 and B2, C1 and C2, or D1 and D2. The first to fourth metric arithmetic operation circuits 1a-1d perform addition or subtraction of the digital signal pairs A1 and A2 to D1 and D2, and output first to fourth operation result values respectively. The maximum likelihood decoder further has a selector 2 and a fifth arithmetic operation circuit 1e. The selector 2 receives a first control signal CL1 indicative of the value of the most significant bit (MSB) of the second operation result value, and a second control signal CL2 indicative of the value of the MSB of the third operation result value. The selector 2 further selects one of the second to fourth operation result values in accordance with the first and second control signals CL1 and CL2 and outputs the selected operation result value to the fifth arithmetic operation circuit 1e. The fifth arithmetic operation circuit 1e has two inputs to respectively receive the first operation result value and one of the second to fourth operation result values. The fifth arithmetic operation circuit 1e performs addition or subtraction of the first operation result value and the operation result value selected by the selector 2, and outputs a fifth operation result value.
However, it is difficult to improve the operation speed of a maximum likelihood decoder equipped with the above-described metric arithmetic operation circuits, for the following reason. The processing from the input of the digital signal pairs A1 and A2 through D1 and D2, to the output of the operation result value from the fifth arithmetic operation circuit 1e, requires the arithmetic operation time and the selector operation time in two stages. After the first and second control signals CL1 and CL2 are produced based on the second and third operation result values, the selector 2 selects one of the second to fourth operation result values according to those control signals CL1 and CL2. The fifth arithmetic operation circuit 1e then performs an operation on the first operation result value and one of the second to fourth operation result values.
If the operation speed of either the second or third arithmetic operation circuit 1b or 1c is slow, the time from the generation of the first and second control signals CL1 and CL2 to the supply thereof to the selector 2 is greater. This delays the selector operation and the arithmetic operation of the fifth arithmetic operation circuit 1e. Consequently, the operation speed of a maximum likelihood decoder having multistage metric arithmetic operation circuits becomes slower. This reduced operation speed affects the operation speed of the overall signal processing system which reads data from a magnetic disk and makes it difficult to improve the recording density of magnetic disks.
An operation test is conducted to check the product reliability of semiconductor integrated circuit devices, including maximum likelihood decoders such as that described above. The operation test for the maximum likelihood decoder supplies a serial signal from a testing device to a digital filter located at the preceding stage of the maximum likelihood decoder from a testing device. The maximum likelihood decoder receives the serial signal from the digital filter and decodes it. The testing device compares the decoded data with the serial signal to determine if the maximum likelihood decoder is operating properly.
In executing the operation test on a fast maximum likelihood decoder, the testing device should supply the serial signal at a high speed. That is, the testing device should also operate at a high speed. However, it is difficult to easily improve the operation speed of the testing device. In the operation test, generally, the internal circuit of a semiconductor integrated circuit device (LSI) operates in accordance with a scan clock signal supplied from the testing device, not a system clock signal. To date, however, the operation test of an LSI which operates in response to a system clock signal having a high frequency, cannot be conducted using a scan clock signal having a lower frequency than the system clock signal. In particular, for a fast LSI equipped with digital and analog circuits, as the ratio of the analog circuits to the digital circuits increases, a sufficient operation test cannot be accomplished with the slow testing device.
A signal processor which processes a read signal read from a magnetic disk includes a user data signal processing circuit, including the aforementioned maximum likelihood decoder, and a servo signal processing circuit. The user data signal processing circuit converts an analog signal, associated with user data included in the read signal, to a digital signal, and then performs a decoding operation on the digital signal and outputs data information to a disk controller. The disk controller extracts user data from the received data information. The servo signal processing circuit processes a servo signal associated with servo control and included in the read signal, and outputs servo information to the disk controller. Based on this servo information, the disk controller controls the drive head to position the head on the target track.
The servo signal processing circuit and user data signal processing circuit share an auto gain control amplifier (AGC) and a filter. The servo signal has a low frequency characteristic and the signal associated with user data has a high frequency characteristic. In this respect, the AGC has both low and high frequency characteristics and the ability to switch between the two. The filter has switchable first and second frequencies, the first one for cutting off a frequency higher than that of the servo signal and the second one for cutting off a frequency higher than that of the signal associated with user data. Under the servo operation, the frequency characteristic of the AGC is switched to the low frequency characteristic and the cutoff frequency of the filter is switched to the first frequency. In a read mode, the frequency characteristic of the AGC is switched to the high frequency characteristic and the cutoff frequency of the filter is switched to the second frequency. The switching of the frequency characteristic of the AGC and the switching of the cutoff frequency of the filter are executed in response to a control signal from the disk controller. However, it takes time to perform switching operation of the AGC and filter, which hinders an improvement to the signal processing speed of the hard disk drive system.
The user data signal processing circuit further includes an A/D converter, which is connected to the filter and converts a read signal that is treated as an analog signal to a digital signal having a plurality of bits. It is desirable that the A/D converter have a characteristic such that the value of the input analog signal and the value of the digital signal are positively proportional to each other. Due to a productional variation, however, some of manufactured A/D converters may have an offset voltage so that a digital value and an analog value are not positively proportional to each other. Using such an A/D converter having an offset voltage, it is difficult to perform highly accurate processing of a read signal supplied from the drive head. Therefore, the offset voltage is canceled either at the time of factory shipment of semiconductor integrated circuit devices, each of which include a signal processing circuit having an A/D converter, or at the time such signal processing circuit is operated. For instance, the offset of an A/D converter may be canceled immediately after the disk drive is powered on.
The long usage of a disk drive increases the temperature of the peripheral circuits of the A/D converter, thus resulting in a variation in the input/output characteristic of the A/D converter. The ratio of the change increases as the ambient temperature increases. This variation undesirably produces an offset voltage again, even though the offset canceling process has been performed once. Moreover, an A/D converter which is designed to output a digital signal having multi-bits (e.g., 6 bits) has a relatively large circuit area. This inevitably increases the circuit area of the associated semiconductor integrated circuit device and hinders improvements on the operation speed and conversion precision of the A/D converter.
Broadly speaking, the present invention relates to a semiconductor integrated circuit device which operates at a high speed.
The invention also relates to a semiconductor integrated circuit device which allows a fast operation test to be performed although a test clock signal has a relatively low frequency.
In addition, the invention relates to a signal processor which processes data signals at a high speed.
The invention further relates to a signal processor capable of canceling an offset voltage of an A/D converter under any circumstances.
The invention also relates to a semiconductor integrated circuit device which prevents a circuit area from increasing and ensures a faster operation speed.
A first embodiment of the invention pertains to a digital arithmetic operation circuit including a plurality of arithmetic operation blocks for receiving a plurality of digital input signals and for performing different arithmetic operations on the received digital input signals, in parallel, to output operation result signals, a control signal generator for receiving a plurality of digital input signals and for generating a control signal based on the digital input signals, and a selector, connected to the plurality of arithmetic operation blocks and the control signal generator, for selecting one of the operation result signals, in response to the control signal, to output the selected operation result signal. After the control signal generator supplies the control signal to the selector, the selector outputs the selected operation result signal as soon as the selected operation result signal is supplied to the selector.
The first embodiment of the invention also pertains to a maximum likelihood decoder including a plurality of arithmetic operation blocks for receiving a plurality of digital input signals and for performing maximum likelihood decoding operations on the received digital input signals, in parallel according to a carry save system, to output decoded signals, a control signal generator for receiving a plurality of digital input signals and for performing an arithmetic operation on the received digital input signals according to a carry look ahead system, to generate a control signal indicative of a most significant bit of an operation result, and a selector, connected to the plurality of arithmetic operation blocks and the control signal generator, for selecting one of the decoded signals in response to the control signal, to output the selected decoded signal.
The first embodiment of the invention further pertains to a semiconductor integrated circuit including an analog equalizer filter for receiving an analog signal and for adjusting a level of the analog signal to output an equalized filtered analog signal, an A/D converter, connected to the analog equalizer filter, for converting the equalized filtered analog signal to a digital signal, a digital filter, connected to the A/D converter, for receiving the digital signal and for removing an unnecessary digital components from the digital signal to output a filtered digital signal, a maximum likelihood decoder, connected to the digital filter, for receiving the filtered digital signal and for performing a maximum likelihood decoding operation on the received filtered digital signal to generate a serial decoded signal, a serial-parallel converter, connected to the maximum likelihood decoder, for converting the serial decoded signal to a parallel decoded signal, and a channel characteristic generator, operatively connected to the maximum likelihood decoder in a test mode, for receiving a test signal supplied from an external testing device and for generating a test version of the filtered digital signal from the test signal, wherein in the test mode, the maximum likelihood decoder receives the test filtered digital signal and performs maximum likelihood decoding thereon.
A second embodiment of the invention pertains to a semiconductor integrated circuit device including an input data holding circuit for temporarily holding an input data signal and for outputting the held input data signal in accordance with a system clock signal, an internal circuit block, connected to the input data holding circuit, for receiving the input data signal and for performing a predetermined data processing operation to output an output data signal in accordance with the system clock signal, an output data holding circuit, connected to the internal circuit block, for temporarily holding the output data signal and for outputting the held output data signal in accordance with the system clock signal, and an external interface circuit connected to the internal circuit block, the input data holding circuit and the output data holding circuit and responsive to a scan clock signal, for generating a test clock signal having a frequency higher than that of the scan clock signal and equal to or higher than that of the system clock signal. The input data holding circuit and the output data holding circuit are operable in accordance with the scan clock signal having a frequency lower than the system clock signal. The external interface circuit supplies the scan clock signal and a test data signal to the input data holding circuit in such a way that the test data signal, as the input data signal, is temporarily held and is output in accordance with the scan clock signal, supplies the test clock signal to the internal circuit block in such a way that the rest data signal is processed in accordance with the test clock signal, and supplies the scan clock signal to the output data holding circuit in such a way that a test result signal, as an output data signal, is temporarily held and is output in accordance with the scan clock signal.
A third embodiment of the invention pertains to a signal processor suitable for processing a user data signal, associated with data information read from a recording medium, and a servo data signal associated with servo information read from the recording medium. The signal processor includes a user data signal processing circuit for processing the user data signal and a servo data signal processing circuit for processing the servo data signal. The user data signal processing circuit includes a first amplifier for amplifying the user data signal to produce an amplified user data signal, and a first filter, connected to the first amplifier, for cutting off an unnecessary frequency component included in the amplified user data signal to produce a filtered amplified user data signal. The servo data signal processing circuit includes a second amplifier for amplifying the servo data signal to produce an amplified servo data signal, and a second filter, connected to the second amplifier, for cutting off an unnecessary frequency component included in the amplified servo data signal to produce a filtered amplified servo data signal.
The third embodiment of the invention also pertains to an integrating circuit for acquiring plural pieces of position data in order to obtain relative positions between tracks to which servo areas provided on a recording medium belong and a drive head moving over the recording medium, each servo area including a plurality of position areas where the position data are respectively recorded. The integrating circuit includes a rectifier for rectifying position data signals read from the position areas to produce rectified position data signals, a voltage-current converter, connected to the rectifier, for producing charge currents having current values proportional to voltage levels of the respective rectified position data signals, a main capacitor, connected to the voltage-current converter, for performing charging with the charge currents, a main charge switch connected between the voltage-current converter and the main capacitor, and operable in such a way as to permit each of the charge currents to be supplied to the main capacitor when each charge current is generated, a main discharge switch, connected to the main capacitor, for permitting charges, stored in the main capacitor, to be discharged after the main capacitor has performed a charging operation, a plurality of detection capacitors, connected to the voltage-current converter, for performing charging with charge voltages respectively associated with the position areas, in cooperation with the main capacitor, the charge voltages of the detection capacitors respectively indicating the plural pieces of position data, a plurality of subcharge switches respectively connected between the voltage-current converter and the detection capacitors and operable in such a way as to permit supply of the associated charge currents to the main capacitor when the charge currents are produced, and a plurality of subdischarge switches, respectively connected to the plurality of subcharge switches, for permitting charges stored in the detection capacitors to be discharged after execution of charging operations of the associated detection capacitors.
A fourth embodiment of the invention pertains to a circuit suitable for canceling an offset voltage of an A/D converter that converts an analog signal to a digital signal. The circuit includes a comparator for receiving the digital signal and for comparing a digital value of the digital signal with a predetermined offset allowance value to output a comparison result, an arithmetic operation unit, connected to the comparator, for accumulating a predetermined offset change amount and outputting an addition result based on the comparison result when the digital value differs from the predetermined offset allowance values, wherein the addition result is initially determined by adding the predetermined offset change amount and a predetermined initial value, and an offset voltage generator, connected to the arithmetic operation unit, for generating an offset cancel voltage in order to cancel the offset voltage in accordance with the addition result and for supplying the offset cancel voltage to the A/D converter.
The fourth embodiment of the invention also pertains to a circuit suitable for canceling an offset voltage of an A/D converter, the A/D converter samples an analog data signal including an analog sinusoidal signal in order to convert the analog data signal to a digital signal. The circuit includes a sampling control circuit for controlling the A/D converter in such a manner that first and third sampling intervals and second and fourth sampling intervals for the analog sinusoidal signal become 180 degrees when the analog sinusoidal signal is supplied to the A/D converter, whereby digital signals having first through fourth digital values are output from the A/D converter in a sampling order, an arithmetic operation unit for receiving one of a set of the first and third digital values and a set of the second and fourth digital values, and for computing an average value thereof to output the obtained average value as an offset voltage value for the A/D converter, and an offset voltage generator for receiving the offset voltage value, for generating an offset cancel voltage to cancel the offset voltage, and for supplying the offset cancel voltage to the A/D converter.
A fifth embodiment of the invention pertains to a semiconductor integrated circuit device including an analog filter for removing an unnecessary frequency component included in an analog signal to produce a filtered analog signal, and an A/D converter, connected to the analog filter, for performing over-sampling of the filtered analog signal according to a first frequency signal to convert the filtered analog signal to a digital signal.
The device of the fifth embodiment may include a first digital filter, connected to the A/D converter, for removing an unnecessary frequency component included in the digital signal in accordance with the first frequency signal to produce a first filtered digital signal, and a digital phase locked loop, connected to the A/D converter and the first digital filter, for generating the first frequency signal and for supplying the first frequency signal to the A/D converter and the first digital filter.
The device of the fifth embodiment may further include a first register, connected to the first digital filter and the digital phase locked loop, for intermittently sampling the first filtered digital signal in accordance with a second frequency signal to produce a first thinned digital signal. The digital phase locked loop may include a voltage controlled oscillator for generating the first frequency signal in response to a voltage signal, and a frequency divider for frequency-dividing the first frequency signal to produce the second frequency signal.
The device of the fifth embodiment may also include a second digital filter, connected to the first sampling register and the digital phase locked loop, for removing an unnecessary frequency component included in the first thinned digital signal in accordance with the second frequency signal to produce a second filtered digital signal.
The device of the fifth embodiment may further include a second register, connected to the second digital filter and the digital phase locked loop, for intermittently sampling the second filtered digital signal in accordance with a third frequency signal to produce a second thinned digital signal. The digital phase locked loop may further include a second frequency divider, connected to the first frequency divider, for frequency-dividing the second frequency signal to produce the third frequency signal.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating the principles of the invention by way of example.